1. Technical Field
The present invention generally relates to transistors for a semiconductor device and methods of fabricating the same.
A claim of priority is made to Korean Patent Application No. 10-2004-0005858, filed Jan. 29, 2004, the contents of which are incorporated by reference in their entirety.
2. Discussion of the Related Art
Conventional semiconductor devices have a transistor. The transistor includes a gate pattern and impurity regions disposed on a semiconductor substrate of the devices. Electrical characteristics of the transistor depend on the gate pattern and the impurity regions. The gate pattern has at least one conductive layer. The conductive layer is formed of a doped polysilicon or a metal silicide stacked on the doped polysilicon. The impurity regions generally refer to source and drain regions of the transistor, and each region is formed by an impurity ion implantation process.
However, impurity ions may diffuse into the gate pattern when the transistor is driven. The diffusion causes a depletion capacitance in the gate pattern. Thus, the depletion capacitance causes a voltage applied to the gate pattern to drop, which delays the immediate voltage transfer to the semiconductor substrate. Further, the voltage may drop as much as the capacitance, thereby deteriorating a driving capability of the transistor. Therefore, even though a gate pattern having a conductive layer is advantageous because it simplifies a fabrication process, a method to suppress the depletion capacitance is required.
U.S. Pat. No. 6,124,177 discloses, for example, a conventional method of fabricating a deep sub-micron MOSFET structure with improved electrical characteristics.
This method discloses forming an arch-shaped gate pattern on a semiconductor substrate. The gate pattern is formed of an undoped polysilicon layer. Ion implantation processes are performed in the semiconductor substrate by using the gate pattern as a mask to form N source and drain areas. The source and drain areas are impurity regions, which overlap the gate pattern. And the source and drain areas produce a gradual concentration gradient in a direction away from the gate pattern.
The method further includes forming gate spacers, which do not cover sidewalls of the gate pattern. That is, air spacers are formed between the gate spacers and the sidewalls of the gate pattern. Using the gate spacers and the gate pattern as a mask, an ion implantation process is used to form N+ source and drain areas in the semiconductor substrate. The conductivity type of the gate pattern is determined during the formation of the N+ source and drain contact areas as well as the source and drain N− areas. Then, a silicidation process is performed on the semiconductor substrate to form a silicide layer on the N+ source and drain areas and the gate pattern.
However, this method forms a silicide layer on the gate pattern. Thus, this method cannot protect against diffusion of impurity ions through the doped polysilicon portion of the gate pattern, which can cause a depletion capacitance. Therefore, a method to suppress the generation of the depletion capacitance is required.